1. Field of the Invention
The present invention relates generally to power supply circuitry and, more particularly, to power-on resets for power supply circuitry.
2. Description of Related Art
Traditionally, an electronic device has required a power supply that provides a relatively constant voltage to the electronic device. In such devices, when power is initially applied to the electronic device, a supply signal increases non-instantaneously from a ground potential to an operational level. When the supply signal exceeds a threshold, a “power-on reset” signal indicates to the various components that sufficient voltage is available on the supply signal. The various components of the electronic device may then initialize to a predetermined state in response to the power-on reset signal. In many electronic devices, each time the power-on reset signal is asserted, the electronic device enters the same predetermined state.
Many electronic devices also have a low power mode, also called a sleep mode or sleep state. When in a low power mode, the supply signal is reduced to a very low level, sufficient to allow some devices to operate but insufficient to allow other components to operate. For example, a computer system may contain a low-power memory that can store session information, recently-modified files, and other data needed to restore the computer system.
When the supply signal is restored to its operational level following a sleep state, it is generally not desirable to assert the power-on reset signal, since the power-on reset signal would return the electronic device to the predetermined state rather than restoring the session. The power-on reset signal might, for example, erase portions of memory that had been used during the session. To avoid this unfortunate result, many electronic devices are designed so that when the voltage of the supply signal increases from the very low “sleep” voltage to a fully operational voltage, the power-on reset signal is suppressed, while when the voltage of the supply signal increases from the ground potential to a fully operational voltage, the power-on reset signal is asserted. Suppressing the power-on reset signal during recovery from a sleep state advantageously prevents re-initialization of memory and other power-on processes that would negate the advantages of the sleep state.
To suppress the power-on reset signal during recovery from a sleep state, various techniques have been used. U.S. Pat. No. 6,084,446 uses two sets of transistors having different threshold voltages. One set of transistors with extremely low threshold voltages is intended to operate even while the computer system is in sleep mode; the gate terminals of these transistors can trigger even when the voltage of the supply signal is very small. The low-threshold transistors provide a non-zero voltage at a node that would be grounded but for the operation of the low-threshold transistors. The other set of transistors, having a normal threshold voltage and having this node at the source terminals, cannot trigger when recovering from the sleep mode but can trigger when recovering from a full power-down state.
Fabricating an integrated circuit with different devices having different threshold voltages can be an expensive and difficult process, possibly requiring multiple mask steps. A need thus exists in the prior art for a power-on reset circuit in which substantially all of the transistors have a uniform threshold voltage, such that the power-on reset circuit can assert a power-on reset signal in response to a supply signal having a sufficient voltage except when recovering from a sleep state. A further need exists for a circuit that generates a power-on reset signal having adequate temperature immunity, ultra-low DC leakage current, and fast power crash reaction.